Since the first integrated circuit, there has been an ever increasing density of devices manufacturable on semiconductor substrates and a corresponding decrease in the size of the integrated circuits. While these advancements have provided better production yields and faster integrated circuits, they have been accompanied by a more complex fabrication process where the size and density make the integrated circuits easily affected by contaminants and process variables.
Well accepted process techniques for fabricating an integrated circuit involves the use of patterning the semiconductor wafer at various levels. These patterns correspond to device regions, or interconnect structures, and such patterns are sequentially transferred to the wafer through well known lithographic processes. The result of each process is a set of features created on the wafer surface. This process can be repeated creating different formations on the wafer or other films and substrates can be applied interconnecting various features until the desire structural configuration is achieved.
The lithographic transfer process begins where layers of photoresist materials are first spin-coated onto the wafer substrate, and then selectively exposed to a form of radiation, such as ultraviolet light. A developer is introduced to the resist which removes parts of the layer made soluble or insoluble by exposure. The patterns in the resist are formed during this "development" step. The areas of resist remaining after development, protect the substrate regions which they cover. Locations from which the resist has been removed can be subjected to a variety of additive (e.g. lift-off) or subtractive (e.g. etching) processes that transfer the pattern onto the substrate surface.
Often, the development step is broken down into four intervals: application, puddle, rinse and dry. During these stages, with the exception of the puddle stage, the wafer is rotating to allow an even distribution of the applied liquid, developer or water rinse. The wafer does not rotate during the puddle interval, allowing the developer to dissolve the soluble portions of the photoresist. Commonly, during the drying interval, the wafer rotates at a higher rate than during the other intervals to remove all liquid. For a better understanding of integrated circuit fabrication, in general, see Silicon Processing for the VLSI Era, Volume 1: Process Technology, by S. Wolf and R. N. Tauber, Lattice Press (1986), which is incorporated herein by reference.
Unfortunately, various problems occur during the fabrication of silicon wafer integrated circuits. One such problem is circular defects, which is a surface imperfection which inhibits chemical etching, and arises from the rinse-related step during the post-development step. During the post-development step, the developer is dissolved and the photoresist is rinsed off the wafer surface allowing access to the substrate below. Problems arise where water, containing developer and resist, is not completely rinsed off the wafer. This solution, containing particulate remains of resist, could land on the exposed silicon substrate where drilling (i.e. etching) was to occur. Subsequently, the etching cannot take place and that portion of the wafer may be unusable, which can substantially affect the production yield, thereby decreasing overall fabrication efficiency and increasing production costs.
Another problem which occurs is the buildup of electrostatic charges in the wafer during fabrication. More specifically, charges will often buildup in films on the semiconductor wafer while the wafer is spinning during various track processes. Charges of this nature, measured in volts per inch, can be extremely destructive to the structures within the wafer. Specifically, these gate oxides, measured in microns, can literally be broken down by these static discharges; a result that is highly undesirable. Commonly, a known manner of attempting to alleviate random electro-static charges includes placing deionizaton bars that produce constant flows of charged ions within the fabrication clean room itself. However, because the clean rooms are typically large, the flow of charge ions often does not reach the device to adequately de-ionize it.
Accordingly, what is needed in the art is a method of semiconductor fabrication which reduces the occurrence of circular defects and electrostatic charge buildup on a semiconductor wafer.